1. Field of the Invention
The present invention relates to a swing limiter and, more particularly, to a swing limiter which is employed in a semiconductor memory device.
2. Description of the Related Art
A typical logic circuit includes at least one pull-up transistor and at least one pull-down transistor. The pull-up transistor is connected to a power voltage and is turned on to generate an output signal at a power voltage level, whereas the pull-down transistor is connected to a ground voltage and is turned on to generate the output signal at the ground voltage level. As a result, the output signal fully swings between the power voltage level and the ground voltage level.
However, a full swing in the output signal can adversely affect high-speed operation, and can increase power consumption. For these reasons, efforts to reduce the swing width have been studied.
FIG. 1 is a circuit diagram illustrating a conventional swing limiter. The swing limiter of FIG. 1 includes a logic circuit 10 having a PMOS transistor P1 and an NMOS transistor N1, an NMOS transistor N2 having a diode configuration, and a PMOS transistor P2 having a diode configuration.
Function of the components of FIG. 1 will now be explained.
The NMOS transistor N2 applies a voltage “VCC−Vtn”, which is obtained by subtracting a threshold voltage Vtn of the NMOS transistor N2 from a power voltage VCC, to the PMOS transistor P1, and the PMOS transistor P2 applies to the NMOS transistor N1 a voltage “VSS+|Vtp|” obtained by adding an absolute value of a threshold voltage Vtp of the PMOS transistor P2 to a ground voltage VSS.
The NMOS transistor N1 is turned on to generate an output signal OUT having a level of “VSS+|Vtp|” when an input signal IN having a high level is applied, and the PMOS transistor P1 is turned on to generate an output signal OUT having a level of “VCC−Vtn” when an input signal IN having a low level is applied. That is, the output signal OUT swings between the voltage “VSS+|Vtp|” level and the voltage “VCC-Vtn” level.
However, without the presence of the NMOS transistor N2 and PMOS transistor P2, the logic circuit 10 generates the output signal OUT having the ground voltage VSS level since the NMOS transistor N1 is turned on when the input signal IN having a high level is applied, and generates the output signal OUT having the power voltage VCC level since the PMOS transistor P1 is turned on when the input signal IN having a low level is applied. That is, in this case, the output signal OUT fully swings between the ground voltage VSS level and the power voltage VCC level.
FIG. 2 shows the swing width of the output signal OUT of the swing limiter. If the swing limiter comprises the logic circuit 10 without the NMOS transistor N2 and the PMOS transistor P2, the swing width is “S1”, whereas if the swing limiter further comprises the NMOS transistor N2 and the PMOS transistor P2 as in the logic circuit of FIG. 1, the swing width of the output signal is reduced to S2.
The conventional swing limiter of FIG. 1 is limited in application, in that it is possible to raise the swing width of the output signal by a level of an absolute value of the threshold voltage of the PMOS transistor or to drop the swing width by a level of the threshold voltage of the NMOS transistor, but it is impossible to raise or drop the swing width by another desired, appropriate, level.
Further, there is a problem in the conventional swing limiter in that the swing level changes as the threshold voltages of the PMOS transistor and the NMOS transistor which include the diode configurations change due to variations in fabrication process, applied voltage or operating temperature.